RP2040 Raspberry Pi RP2040 Microcontroller: dual-core M0+ up to 133 MHz, 264 kB SRAM, USB 1.1

Raspberry Pi RP2040 MCU – Detailed Overview & Specifications

The Raspberry Pi RP2040 is a high-performance, low-cost microcontroller designed to bridge powerful embedded capabilities with exceptional ease of use. At its heart are two Arm® Cortex®-M0+ cores that can run at up to 133 MHz, backed by 264 kB of on-chip SRAM arranged in multiple banks for parallel access and deterministic throughput. Code executes from external QSPI flash using a hardware XIP path with caching, so you can size non-volatile storage to your application without sacrificing performance. A rich set of on-chip peripherals—two UARTs, two SPI, two I²C, 16 PWM channels, a 12-bit 4-channel ADC (with internal temperature sensor), USB 1.1 device/host, plus two PIO blocks with eight state machines total—enables both classic embedded designs and custom digital interfaces that would normally require external logic.

Beyond the headline features, RP2040’s internal architecture offers a fully connected AHB crossbar and DMA engines to offload data movement, reducing CPU load and jitter. Programmable I/O (PIO) delivers deterministic, cycle-exact control over pins, letting you “create” peripherals such as custom UARTs, DVI/parallel video, precise WS2812 (NeoPixel) drivers, or protocol shims—all in silicon, without additional hardware.

RP2040 also excels at power management. It supports sleep and dormant modes that gate clocks aggressively and even stop oscillators for near-zero dynamic power, while preserving system state and allowing wake from GPIO or RTC (with an external clock source). This enables multi-year battery-powered products when combined with careful system design.

Why RP2040 for your design?

• Performance headroom from dual cores and fast SRAM, with code XIP from affordable QSPI flash.

• Extraordinary I/O flexibility from PIO, covering those “odd-ball” buses and tight timing tasks in software-defined hardware.

• Mature tooling (C/C++ and MicroPython) and extensive examples that shorten bring-up and time-to-market (supported in the official SDK and examples referenced throughout the datasheet).

Specifications

• Citations for the table entries: CPU/SRAM/Peripherals/USB/PIO/ADC/Flash (XIP) and GPIO counts come from the chip summary and key features.
• External flash/XIP and cache details, and debug:
• On-chip extra RAM (XIP cache/USB DPRAM) totaling 284 kB:
• Low-power SLEEP/DORMANT behavior:
• Power-supply rails and ranges:
• USB host/device controller with integrated PHY:
• GPIO/ADC mapping, QSPI, crystal, SWD, RUN/TESTEN, USB pins, supply pins:
• Package, footprint, compliance:

Applications

• Consumer and Maker Products – Build keyboards, game controllers, MIDI instruments, sensor hubs, wearables, and lighting projects. RP2040’s abundant GPIO, PWM, and ADC channels simplify signal interfacing, while PIO handles timing-critical protocols (e.g., one-wire LEDs) entirely in hardware-like fashion.

• Industrial & Commercial – Implement protocol bridges (UART-to-RS485 with precise timing, legacy bus translators), high-reliability motor/valve control loops using PWM and ADC feedback, or USB-connected tools. Deterministic bus fabric and DMA minimize jitter in control paths.

• Human-Machine Interfaces – Capacitive or resistive input reading, LED/LCD driving via PIO (parallel or serialized protocols), and responsive UI logic on one core while I/O streaming runs on the other core.

• Connectivity & Custom Peripherals – Use PIO to generate additional UARTs/SPI-like links or translate unusual sensor buses; scale baud/frequency precisely with state-machine clock dividers.

• Audio & Media – Leverage I²S-like signaling with PIO for DAC/codec interfacing, or run USB Audio Device with the integrated PHY, while DMA streams samples between memory and peripherals with minimal CPU intervention.

• Low-Power/Remote Sensing – Sleep the system aggressively between measurements; wake on GPIO or RTC tick in DORMANT mode for ultra-low energy duty cycles.

Design Notes & Benefits

• Flexible Flash Choices: RP2040 is intentionally “stateless,” booting from external SPI/QSPI flash via XIP, so you choose the density, speed grade, and cost point that fit your bill of materials. The Boot ROM even exposes commands to enter/exit XIP for robust flashing over USB.

• Robust Power Domains: Separate rails for core, I/O, USB, and ADC help meet noise and accuracy goals. The ADC, for instance, prefers ≥ 2.97 V for best performance.

• Developer-Friendly: SWD debug, polished C/C++ and MicroPython support, and extensive code examples for PIO (e.g., square-wave, UART TX/RX, logic analyzer) shorten ramp-up dramatically.

Three Key Highlights

1. Dual-core performance with ample SRAM – Two M0+ cores up to 133 MHz and 264 kB multi-bank SRAM keep control loops, UI, and I/O running smoothly in parallel.

2. Programmable I/O (PIO) – Two PIO blocks (eight state machines) provide cycle-accurate pin control to emulate or extend peripherals like UART, video, or bespoke serial protocols—without extra ICs.

3. Rich connectivity including USB 1.1 – Integrated full-speed USB with device/host modes, two each of UART/SPI/I²C, 16 PWM channels, 12-bit ADC, and 30 GPIO unlock a wide array of products with minimal components.

Extended Description

RP2040’s memory system is engineered for throughput and predictability. The 264 kB SRAM is split into large striped banks plus two smaller 4 kB banks, allowing multiple masters (e.g., CPU0, CPU1, DMA, USB) to access different banks simultaneously with reduced contention. For demanding workloads, developers can place hot code or stacks in dedicated regions or even use the 16 kB XIP cache as scratch RAM when executing from SRAM, and repurpose the 4 kB USB DPRAM when USB isn’t required. Taken together, on-chip RAM can reach up to 284 kB under those conditions.

Clocking options cover both accuracy and speed. A ring oscillator (ROSC) starts automatically at boot and can clock the cores directly, but for accurate timing (USB, ADC, RTC) you should switch to the external crystal oscillator (XOSC) and PLLs. Software can safely enter and exit deep-sleep states—SLEEP and DORMANT—while retaining state and waking on interrupts, GPIO events, or RTC alarms (with an external clock source).

On the electrical side, the device specifies independent rails and ranges for IO, core, regulator input/output, USB PHY, and ADC, ensuring you can optimize analog performance and USB compliance. Multiple IOVDD/DVDD pins and a central ground pad support low-impedance power distribution on compact, cost-optimized PCBs.

Pin-level resources include 30 multi-function GPIO (GPIO0–GPIO29), four of which double as ADC inputs (GPIO26–GPIO29), dedicated QSPI pins for external flash, crystal pins (XIN/XOUT), SWD pins for debug, and USB D+/D− (with 27 Ω series resistors). The RUN pin supports external enable/reset control.

Mechanically, RP2040 ships in a 56-pin QFN with an exposed center pad. The package is MSL-1 and compliant with RoHS and REACH. Pay attention to the note that the center pad is smaller than many generic QFN-56 footprints—adjust your land pattern accordingly for robust assembly and routing between pad and perimeter pins.

In short, RP2040 condenses the versatility of a small FPGA-plus-MCU design into a single, affordable microcontroller: ample processing, fast deterministic memory, flexible I/O via PIO, modern USB, and sophisticated power management—backed by first-class documentation and examples.

Use-Case Examples

• Custom Serial Bridges: Build multiple software-defined UARTs at unique baud rates on different pins with PIO, while DMA streams data to and from memory.

• Precision LED/Signal Control: Generate cycle-exact waveforms and neatly timed protocols (e.g., WS2812, precise PWM shaping, stepper control) under PIO control.

• USB Tools: Create USB devices (HID, CDC, MSC) or even a simple host for low-speed devices, leveraging the integrated PHY and SIE registers documented in detail.