ESP32-C5 ESPRESSIF ESP32-C5 Wi-Fi 6 + Bluetooth LE + 802.15.4 MCU
- Tri-radio on one chip: Dual-band Wi-Fi 6 + BLE 5 + IEEE 802.15.4 for Thread/Zigbee in a single, compact MCU.
- Security built-in: Secure boot, XTS-AES memory encryption, HMAC, RSA/ECC/ECDSA, TRNG, APM & PMP hardening—ready for zero-trust IoT.
- Designed for battery life: LP RISC-V core, deep-sleep with LP SRAM retention, Wi-Fi TWT, and fine-grained PMU control.
In Stock
Request a QuoteESP32-C5 Specifications & Key Features Applications
ESPRESSIF’s ESP32-C5 is an ultra-low-power SoC built around a 32-bit RISC-V architecture and purpose-designed for modern, connected IoT. It uniquely combines dual-band Wi-Fi 6 (2.4/5 GHz), Bluetooth® 5 Low Energy, and IEEE 802.15.4 (Thread 1.4/Zigbee 3.0) with a rich set of digital/analog peripherals, strong security primitives, and flexible power management.
Inside, you’ll find a high-performance RISC-V core (up to 240 MHz) for application workloads plus an always-available low-power RISC-V core (up to 40/48 MHz) to manage deep-sleep tasks, wakeups, and sensor housekeeping. The radio subsystem supports OFDMA, TWT, MU-MIMO (downlink), spatial reuse and beamformee operation to deliver resilient, efficient links in dense deployments. A comprehensive security block—secure boot, XTS-AES flash/PSRAM encryption, TRNG, HMAC, RSA/ECC/ECDSA accelerators, Access Permission Management (APM) and Physical Memory Protection (PMP)—protects code, data, and transport. The device exposes 29 GPIOs and a wide peripheral set including USB Serial/JTAG, CAN FD, I2S, I2C (plus LP-I2C), SPI (with quad-SPI memory interface), ADC, LEDC PWM, MCPWM, RMT, GDMA, and a parallel IO engine.
According to the functional block diagram (page 2), ESP32 C5 integrates RF, baseband/MAC for Wi-Fi/BT/802.15.4, power management, system timers, DMA, and security engines on one die, with provision for external flash/PSRAM to scale memory as needed. A compact QFN48 (6 × 6 mm) package simplifies dense layouts.
Specifications
| Item | Details |
|---|---|
| CPU | High-Performance 32-bit RISC-V up to 240 MHz (5-stage pipeline); Low-Power 32-bit RISC-V up to 40/48 MHz for deep-sleep tasks. |
| Instruction set | RV32IMAC with Zc extensions; HW loop; CLINT/CLIC; up to 3 breakpoints; PMP/PMAs. |
| Memory (internal) | 320 KB ROM; 384 KB HP SRAM; 16 KB LP SRAM; eFuse 4 Kbit (1,792 bits user). |
| External memory | SPI/Dual/Quad/QPI flash & PSRAM; up to 32 MB mapped; XTS-AES on-the-fly encryption/decryption. |
| Wireless – Wi-Fi | Dual-band 2.4/5 GHz 802.11a/b/g/n/ac/ax; 1T1R; OFDMA UL/DL; DL MU-MIMO; TWT; beamformee; 20 MHz BW; up to 150 Mb/s (11n). |
| Wireless – Bluetooth LE | Bluetooth Core 6.0 certified LE: 125 kb/s, 500 kb/s, 1 Mb/s, 2 Mb/s; PA up to 20 dBm; AoA/AoD; PAwR; LE power control; multiple roles concurrently; mesh 1.1. |
| Wireless – 802.15.4 | 2.4 GHz O-QPSK; 250 kb/s; Thread 1.4 & Zigbee 3.0 capable; HW CSMA/CA, auto-ACK/frame-pending. |
| Antenna pins | ANT_2G (2.4 GHz) & ANT_5G (5 GHz) RF I/O; supports antenna diversity via external RF switch controlled by GPIOs. |
| Peripherals | 2× UART + LP-UART; 2× SPI for flash/PSRAM + GP-SPI; I2C + LP-I2C; I2S (TDM/PDM/PCM); USB 2.0 FS Serial/JTAG; 2× CAN FD; SDIO-Slave; LED PWM (6 ch); MCPWM (6 ch); RMT (2 TX + 2 RX); PARLIO (1/2/4/8-bit); GDMA (3 TX + 3 RX); BitScrambler; PCNT; timers; WDTs. |
| Analog | 12-bit SAR ADC (up to 6 channels); on-chip temperature sensor; analog voltage comparator; brownout & power-glitch detectors. |
| GPIO count | 29 GPIOs; flexible IO-MUX/GPIO Matrix; LP-IO for deep-sleep; see consolidated pin overview (Appendix A). |
| Security | Secure boot; XTS-AES flash/PSRAM encryption; AES-128/256, SHA-1/2/384/512, RSA (up to 3072 bits), ECC (P-192/256/384), ECDSA accelerator; HMAC; TRNG; APM & TEE controls; PMP; power-glitch detector. |
| Power modes | Active / Modem-sleep / Light-sleep / Deep-sleep; LP core + LP SRAM remain in deep-sleep; TWT for Wi-Fi power savings. |
| Typical current (guide) | Deep-sleep ≈ 12 µA; light-sleep ≈ 0.25 mA; 2.4 GHz RX ≈ 99–107 mA; 5 GHz RX ≈ 127–135 mA (conditions in datasheet). |
| TX power (typ.) | Wi-Fi 2.4 GHz up to 20 dBm (1 Mb/s CCK); 5 GHz up to 19 dBm (6 Mb/s). Bluetooth LE up to 20 dBm. 802.15.4 up to 20 dBm. |
| Supply & I/O | Single 3.0–3.6 V rails across VDDA/VDDPST; internal 1.1 V regulators; VDD_SPI for external memories; see power scheme (page 27). |
| Package | QFN48, 6 × 6 mm; –40 °C to +105 °C (ESP32-C5HR8) and other variants as listed. |
| Notable diagrams | Block diagram (page 2), pin layout (page 16), power-up/reset timing & scheme. |
Applications
Smart Home & Building:
Thread/Zigbee sensors and actuators, dual-band Wi-Fi 6 gateways, multi-protocol bridges (Wi-Fi ↔ BLE/Thread), connected switches, meters, security panels, voice assistants (I2S audio front ends).
Industrial & Commercial:
Low-power telemetry nodes, asset trackers, condition-monitoring sensors, barcode/POS terminals (USB Serial/JTAG for simple service access), CAN-FD edge devices, data loggers with external PSRAM/flash.
Healthcare & Wearables:
BLE-centric devices with long-range coded PHY (125/500 kb/s), beacons with PAwR, gateways that aggregate BLE and 802.15.4 to backhaul over Wi-Fi 6.
Consumer & Robotics:
Dual-band Wi-Fi-controlled appliances, service robots leveraging MCPWM for motors, RMT for IR remote, and LEDC for RGB lighting effects.
Audio & Media:
I2S/TDM/PDM interfaces for mics/codecs, GDMA for low-jitter streaming, PARLIO for camera-like parallel interfaces.
Developer-friendly products:
USB Serial/JTAG (no external probe) for programming and debugging, plus ESP-IDF support and comprehensive documentation.
Design notes & integration tips
-
RF & layout: Two dedicated RF pads (ANT_2G/ANT_5G). For small enclosures or boards with hand effects, consider an external RF switch and use antenna diversity (GPIO-controlled) as highlighted under Wi-Fi radio.
-
Memory mapping: Map external flash/PSRAM into instruction/data address space in 64-KB blocks; enable XTS-AES to protect code and variables transparently.
-
Power domains: The PMU powers HP/LP/Analog domains independently. The diagram on page 27 shows the rails and internal LDOs; keep CHIP_PU and power-up timing per Table 2-11 for reliable boots.
-
Pins & multiplexing: IO-MUX/GPIO Matrix offer great flexibility; consult the consolidated pin table and highlighted restrictions (flash PSRAM pins, JTAG/USB/SDIO overlap, strapping pins) before routing. The pin layout is on page 16; the consolidated overview is Appendix A.
-
Security provisioning: Use eFuse for keys and configuration; note eFuse is one-time programmable. Enable secure boot and memory encryption early in your production flow.
Why ESP32-C5 for your next design?
It’s a single-chip platform that eliminates external co-processors and bridges: tri-radio connectivity, ample peripherals, and serious security are all on-die. You can prototype quickly with ESP-IDF, scale with external flash/PSRAM, and ship in a tiny QFN package with robust power-save features to hit aggressive battery targets. The result: smaller BOM, simpler certification strategy, and a future-proof network stack spanning Wi-Fi 6, BLE 5, and 802.15.4.
Specification: ESPRESSIF ESP32-C5 Wi-Fi 6 + Bluetooth LE + 802.15.4 MCU
|
